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Si550
Rev. 0.5
5
Table 7. CLK± Output Phase Noise (Typical)
Configuration
fC
KV
Output
74.25 MHz
45 ppm/V
CMOS
300 MHz
90 ppm/V
LVPECL
622.08 MHz
45 ppm/V
LVPECL
Units
Offset Frequency (f)
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
L (f)
dBc/Hz
–94
–117
–128
–135
–138
–143
n/a
–74
–98
–112
–122
–134
–144
–147
–77
–101
–114
–118
–128
–144
–147
Table 8. Absolute Maximum Ratings
Parameter
Symbol
Rating
Units
Supply Voltage
VDD
–0.5 to +3.8
Volts
Input Voltage
VI
–0.5 to VDD + 0.3
Volts
Storage Temperature
TS
–55 to +125
C
ESD Sensitivity (HBM, per JESD22-A114)
ESD
>2500
Volts
Soldering Temperature (lead-free profile)
TPEAK
260
C
Soldering Temperature Time @ TPEAK (lead-free profile)
tP
10
seconds
Note: Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions.
Table 9. Environmental Compliance
The Si550 meets the following qualification test requirements.
Parameter
Conditions/ Test Method
Mechanical Shock
MIL-STD-883F, Method 2002.3 B
Mechanical Vibration
MIL-STD-883F, Method 2007.3 A
Solderability
MIL-STD-883F, Method 203.8
Gross & Fine Leak
MIL-STD-883F, Method 1014.7
Resistance to Solvents
MIL-STD-883F, Method 2016
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